The present invention relates to a regulator circuit, and more particularly, to reducing output noise when switching between a switching regulator and a linear regulator.
FIG. 1 is a schematic block diagram of a conventional regulator circuit 10. The regulator circuit 10 includes a linear regulator 12 and a switching regulator 14, each supplied with input voltage VIN from a power supply.
The linear regulator 12 is a low dropout (LDO) circuit that generates a first regulator voltage OUT1 having substantially the same level as the input voltage VIN. The linear regulator 12 includes a p-channel MOS transistor T1, which receives the input voltage VIN, and feeds back the first regulator voltage OUT1 output from the transistor T1 to an error amplifier 20 via a node N1 connecting resistors 16 and 18. The error amplifier 20, which is activated by an enable signal LDOEN, compares the first regulator voltage OUT1, which is received via a feedback loop FB1, with a reference voltage Vref. The error amplifier 20 generates a drive voltage V1 for driving the transistor T1 to compensate for fluctuations in the first regulator voltage OUT1 based on the comparison result of the voltages OUT1 and Vref.
The switching regulator 14 is a DCDC converter (also referred to as DDC) that includes a p-channel MOS transistor T2, which receives the input voltage VIN, and an n-channel MOS transistor T3, which is connected between the transistor T2 and ground. The switching regulator 14 controls the on-duty cycle of the transistors T2 and T3 to charge current to a coil L1, which is connected to a node N2 between the transistors T2 and T3, and accumulates charge corresponding to the current in a capacitor C1. In this manner, the switching regulator 14 generates a substantially constant stable second regulator voltage OUT2. The switching regulator 14 feeds back the second regulator voltage OUT2 to a DCDC control circuit 22 via a feedback loop FB2 (coil L1).
The DCDC control circuit 22 includes an error amplifier 22A and a signal processing circuit 22B, which are activated by an enable signal DDCEN. The error amplifier 22A compares the second regulator voltage OUT2 with a target voltage, that is, a reference voltage supplied to the error amplifier 22A, and generates an amplification signal corresponding to the comparison result. The signal processing circuit 22B, which includes an oscillator and a PWM comparator (not shown), generates a pulse signal SP by combining the oscillation signal of the oscillator and the amplification signal of the error amplifier 22A with the PWM comparator. A pre-driver 24 uses the pulse signal SP to generate drive signals VH and VL for respectively driving the transistors T2 and T3. The DCDC control circuit 22 thus controls the transistors T2 and T3 to maintain the second regulator voltage OUT2 at the target voltage.
The regulator circuit 10 generates an output voltage OUT using one of the first regulator voltage OUT1, which is generated by the linear regulator 12, and the second regulator voltage OUT2, which is generated by the switching regulator 14. The regulator circuit 10 supplies the output voltage OUT to an internal circuit (not shown) as operational power.
The feedback loop FB2 of the switching regulator 14 is connected to the feedback loop FB1 of the linear regulator 12. Thus, the feedback loop FB2 of the switching regulator 14 is affected by the first regulator voltage OUT1 when switching the output voltage OUT of the regulator circuit 10 from the first regulator voltage OUT1 to the second regulator voltage OUT2. This problem will now be described with reference to FIGS. 2 and 3.
FIG. 2 is a timing chart showing an output switching sequence of the regulator circuit 10. During period t1, the linear regulator 12 is activated by the enable signal LDOEN having an H level, and the switching regulator 14 is inactivated by the enable signal DDCEN having an L level.
At time t2, the enable signal LDOEN falls, and the enable signal DDCEN rises. Therefore, the linear regulator 12 is inactivated. Simultaneously, the switching regulator 14 is activated. Specifically, the DCDC control circuit 22 is activated, and the transistors T2 and T3 operate in response to the drive signals VH and VL. As a result, the current corresponding to the input voltage VIN charges the coil L1, and the second regulator voltage OUT2 gradually rises.
The current does not charge the coil L1 when the switching regulator 14 is initially activated. In such a case, in the conventional regulator circuit 10, a voltage drop (noise) occurs in the output voltage OUT, as shown in FIG. 2.
FIG. 3 is a timing chart showing another output switching sequence of the regulator circuit 10. At time t3, the enable signal DDCEN rises so that the linear regulator 12 and the switching regulator 14 are both activated. Subsequently, at time t4, the enable signal LDOEN falls and the linear regulator 12 is inactivated. That is, the linear regulator 12 is driven together with the switching regulator 14 in an overlapping manner during the period of time t3 to t4.
Japanese Laid-Open Patent Publication No. 2005-198484 discloses such overlap control. However, even when the overlap control shown in FIG. 3 is executed, output noise may be produced by offsets in the error amplifier 22A caused by manufacturing variations. Such output noise may be generated due to the reference voltage (i.e., target voltage) of the error amplifier 22A being lower than the originally intended target voltage (designed voltage). In this case, the feedback voltage (substantially, voltage OUT1) supplied to the error amplifier 22A via the feedback loop FB2 would be higher than the target voltage. Therefore, the signal processing circuit 22B generates the pulse signal SP to lower the second regulator voltage OUT2. As a result, voltage drop (undershoot) occurs in the output voltage OUT of the regulator circuit 10.
Japanese Laid-Open Patent No. 2005-130622 discloses a switching regulator in which capacity is lowered from that for normal operation when switching from a linear regulator to the switching regulator in order to prevent undershoot. However, such method lowers the activation speed of the switching regulator.